Performance-oriented placement and routing for field-programmable gate arrays | IEEE Conference Publication | IEEE Xplore

Performance-oriented placement and routing for field-programmable gate arrays


Abstract:

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placemen...Show More

Abstract:

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wire-length. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks.
Date of Conference: 18-22 September 1995
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-7156-4
Conference Location: Brighton, UK

References

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