Abstract:
With the scaling of the power supply voltage V/sub DD/ in low voltage and low power VLSI, the threshold voltage of the MOSFET device needs to be reduced to retain the dev...Show MoreMetadata
Abstract:
With the scaling of the power supply voltage V/sub DD/ in low voltage and low power VLSI, the threshold voltage of the MOSFET device needs to be reduced to retain the device performance in terms of current driving capability and switching speed. Recently MOSFET devices whose threshold voltages can be adapted during the transistor operation using the body effect have been proposed for low voltage and low power VLSI applications. In these devices, the threshold voltages are reduced by forward-biasing the body-to-source junction. In this paper we study the effect of the channel doping engineering on this threshold voltage reduction scheme.
Published in: 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers
Date of Conference: 31 May 1995 - 02 June 1995
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-2773-X
Print ISSN: 1524-766X
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1.
D. Takashima, S. Watanabe, H. Nakano, Y. Oowaki, K. Ohuchi and H. Tango, "Standby/Active Mode Logic for Sub-IV Operating ULSI Memory", IEEE Journal of Solid State Circuits, vol. 29, no. 4, pp. 441, April 1994.
2.
A. P. Chankrakasan, A. Burstein and R. W. Broaderson, "A Low-Power Chipset for a Portable Multimedia I/O Terminal", IEEE Journal of Solid State Circuits, vol. 29, no. 12, pp. 1415, December 1994.
3.
M. Horowitz, T. Indemaur and R. Gonzalez, "Low-Power Digital Design", 1994 IEEE Symposium on Low-Power Electronics Digest of Technical Papers.
4.
F. Assaderaghi, S. Parke, P. Ko and C. Hu, "A Novel Siliconon-Insulator MOSFET for Ultra Low Voltage Operation", 1994 IEEE Symposium on Low-Power Electronics Digest of Technical Papers.
5.
T. Andoh, A. Furukawa and T. Kunio, "Design Methodology for Low-Voltage MOSFET's", IEDM Technical digest, pp. 79.
6.
K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K. Nakajima, H. Miyamoto, et al., "0.1μm Delta-Doped MOSFET Using Post Low-Energy Implanting Selective Epitaxy", 1994 Symposium on VLSI Technology Digest of Technical Papers.
