Single Event Effects on Static and Clocked Cascade Voltage Switch Logic (CVSL) Circuits | IEEE Journals & Magazine | IEEE Xplore

Single Event Effects on Static and Clocked Cascade Voltage Switch Logic (CVSL) Circuits


Abstract:

In order to design radiation-hardened LSIs for space applications, single event transient upset effects on cascade voltage switch logic (CVSL) circuits have been investig...Show More

Abstract:

In order to design radiation-hardened LSIs for space applications, single event transient upset effects on cascade voltage switch logic (CVSL) circuits have been investigated using SPICE. Static and clocked CVSL test circuits have been successfully fabricated utilizing a double polysilicon double metal N-well CMOS technology. Both CVSL circuits have been confirmed to function correctly by the fabricated chip measurements. SET simulation results have confirmed that the CVSL circuits have increased tolerance to SET. SET tolerance for the CVSL circuits is compared to that for the conventional CMOS circuits, showing that the CVSL is a candidate for a SET tolerant spaceborne logic circuit. Furthermore, the static CVSL and clocked CVSL are compared.
Published in: IEEE Transactions on Nuclear Science ( Volume: 56, Issue: 4, August 2009)
Page(s): 1987 - 1991
Date of Publication: 18 August 2009

ISSN Information:


I. Introduction

Single event effects and phenomena are a well-known problem for electronic systems operating in a radiation environment [1]. Pulses of ionizing radiation are known to be effective in corrupting the information integrated circuits store [2]– [4]. In the galactic cosmic ray environment typical of high altitude satellite orbits, a single event upset (SEU), which occurs when a charged particle passing through a cell deposits enough energy for the cell to change its state, should be taken into account.

References

References is not available for this document.