I. INTRODUCTION
With the rapid development of VLSI technology and the complexity of VLSI circuits, interconnects are becoming one important factor for the performance of the chips and interconnect analysis is challenging CAD [1]. Conventional methods for interconnect analysis are impractical. Now, one efficient way to solve the above difficulties is model reduction. By transforming the large matrix into one smaller matrix, the response of the large network can be approximated by the response of the small network which can be calculated easily. Many algorithms have been proposed for model reduction [1]. Generally, they can be grouped into two kinds. The first is direct MMT (Moment Matching Technique) based on AWE (Asymptotic Waveform Evaluation) technique [2] and the second is implicit MMT based on Krylov subspace [3] [4] [5]. However, for the former, the passivity of the reduced network can not be guaranteed. For the latter, model reduction is completed in the frequency domain and inverse Laplace transformation or inverse fast Fourier transformation is needed to get the response in the time domain. Recently, new methods are proposed for model reduction, such as [6] and [7].