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A Performance-Enhancing Fault-Tolerant Routing Algorithm for Network-on-Chip in Uniform Traffic | IEEE Conference Publication | IEEE Xplore

A Performance-Enhancing Fault-Tolerant Routing Algorithm for Network-on-Chip in Uniform Traffic


Abstract:

This paper proposes a performance-enhancing fault-tolerant routing algorithm based on f-cube3 as a new solution for increasing the rate of switched and routed packets in ...Show More

Abstract:

This paper proposes a performance-enhancing fault-tolerant routing algorithm based on f-cube3 as a new solution for increasing the rate of switched and routed packets in NoCs. The f-cube3 algorithm is a wormhole-switched routing for 2-D mesh networks and has been used for block faults such as f-ring and f-chain. We have enhanced the use of virtual channels per each physical link without adding new extra virtual channel. It is proposed that when a message is not blocked by fault, all virtual channels could be used. We have simulated both f-cube3 and our algorithm for the same conditions; message length, network size, traffic etc. As the simulation results show, our algorithm has a higher saturation point than f-cube3 algorithm. The results also show that our algorithm has more utilization of links and less blocked messages rate than f-cube3.
Date of Conference: 25-29 May 2009
Date Added to IEEE Xplore: 12 June 2009
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ISSN Information:

Conference Location: Bundang, Indonesia

1. Introduction

Interconnecting the existing components of chips and appropriate design and process technologies are the main causes of progress in SoC design. On-chip physical interconnections will present a limiting factor for performance. Synchronization of future chips with a single clock source and negligible skew are other challenges; however, they would be possible with GALS (Globally Asynchronous Locally Synchronous) paradigm. Since global control of information traffic between components is very difficult and needs to keep track of each component's states, components will initiate data transfers autonomously - according to their needs. As SoC complexity scales, capturing the system's functionality with fully deterministic operation models will become increasingly difficult. Henceforth, SoC design should separate the computation from communication, as they are orthogonal issues [2].

References

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