1 Introduction
NETWORKs-ON-CHIP (NoC) architectures are becoming the de facto fabric for both general-purpose chip multi-processors and application-specific systems-on-chip designs. In the design of NoCs, high throughput and low latency are both important design parameters and the router microarchitecture plays a vital role in achieving these performance goals. High throughput routers allow a NoC to satisfy the communication needs of multi- and many-core applications, or the higher achievable throughput can be traded off for power savings by using fewer resources to attain a target bandwidth. Ultimately, a router's role lies in the efficient multiplexing of packets onto network links.