Contents I. Introduction
In Double gate field effect transistors there is strong coupling between the surface potentials of two gates before channel formation; as a result back gate biasing is used conventionally to control the threshold voltage of these types of transistors [1]. This is a type of dynamic control method. After channel formation the dependence between surface potentials will be removed and the increase in the threshold voltage will be vanished. Because of high speed operation and large switching activity factor, domino logic circuits mainly work at high temperature conditions. Subthreshold current is exponentially dependent in temperature, thus the static power consumption of domino logics will be high, also by scaling down of DGFET devices to 32nm technology node the static power becomes comparable with dynamic power consumption. Recently the effectiveness of control method by means of back gate biasing has been investigated [2]. Design of domino logic using double gate transistors has been investigated in [3], [4]. In this paper we investigate the trade offs between power and speed for -control scheme, conventional scheme and a method presented in [3] for domino logics.
