Compound Semiconductor as CMOS Channel Material: Déjà vu or New Paradigm?

We have examined the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (V_CC). Based on the two-dimensional numerical drift-diffusion simulations, we conclude that 30 nm gate length InAs (indium arsenide) based TFETs can achieve I_on/I_off of > 4x10⁴ with < 1 ps intrinsic delay at 0.25 V V_CC. In fact, the InAs TFETs show the maximum benefit when their supply voltage V_CC is scaled aggressively down to 0.25 V and this benefit primarily arises from a) efficient tunneling under low electric field and b) their higher source-side injection velocity. MOSFETs or quantum-well FETs in this low V_DD range do not even meet the I_on-I_off stipulation of 10⁴.

Continued miniaturization of silicon CMOS technology, has resulted in an unprecedented increase in single-core and multi-core performance of modern-day microprocessors. However, the exponentially rising transistor count on a single chip has also increased the power consumption, making performance per watt as the key figure-of-merit for today's high-performance microprocessors. Today, energy efficiency serves as the very central tenet of high performance microprocessor technology at both the system architecture level as well as the discrete transistor level. Aggressive supply voltage scaling while maintaining the transistor performance is an obvious route to reducing the overall power dissipation. To that effect, compound semiconductor-based quantum-well (QW) transistors as well as interband tunnel transistors provide a promising device option, since III—V semiconductors (e.g. Indium antimonide, Indium arsenide and ) have excellent low-field and high-field electron transport properties as well as narrow and direct gaps resulting in high-speed switching at very low supply voltages.