A dynamically reconfigurable Field Programmable Gate Array hardware foundation for security applications

As field programmable gate arrays (FPGAs) become more widely used, security concerns have been raised regarding FPGA use for cryptographic, sensitive, or proprietary data. Storing or implementing proprietary code and designs on FPGAs could result in the compromise of sensitive information if the FPGA device was physically relinquished or remotely accessible to adversaries seeking to obtain the information. A hardware description language (HDL) FPGA architecture supporting dynamic reconfiguration through granular reconfiguration control is presented for use in security applications. Testing validates the reconfiguration results and compares power usage, timing, and area estimates from a conventional and Dynamically Reconfigurable FPGA (DRFPGA) model.

1. Introduction

Sensitive or proprietary designs on FPGA platforms are vulnerable to exploitation and/or theft due to inherent insecurities in the FPGA design. Although multiple defensive measures have been implemented (and overcome) for FPGA designs, the possibility exists to create a secure design through the implementation of DRFPGA circuits. Using a DRFPGA removes the static attributes from their design; thus, substantially increasing the difficulty of successful reverse-engineering attacks.