Path Delay Fault Test Set for Two-Rail Logic Circuits | IEEE Conference Publication | IEEE Xplore

Path Delay Fault Test Set for Two-Rail Logic Circuits


Abstract:

Two-rail logic circuits can be efficiently tested by non-codeword vector pairs. However, non-codeword vector pairs may sensitize some path delay faults which affect neith...Show More

Abstract:

Two-rail logic circuits can be efficiently tested by non-codeword vector pairs. However, non-codeword vector pairs may sensitize some path delay faults which affect neither normal operation nor strongly fault secure property of the two-rail logic circuits. It means that testing with non-codeword vector pairs may be over-testing. This paper presents a construction of robust path delay fault test sets for two-rail logic circuits. The proposed test sets do not lead to the over-testing.
Date of Conference: 15-17 December 2008
Date Added to IEEE Xplore: 22 December 2008
CD:978-0-7695-3448-0
Conference Location: Taipei, Taiwan

1: Introduction

In the recent and future high-density and low-power VLSIs, soft and hard errors frequently occur during system operation. In addition, VLSIs become sensitive to noise and thus it becomes difficult to achieve good signal integrity[1], [2], [3]. So, redundant technologies for improving dependability become increasingly important. Two-rail logic (TRL) circuit design is a well-known class of redundant designs for logic circuits providing strongly fault secure (SFS) property for unidirectional stuck-at faults[4], [5], [6]

Note that the targeted TRL circuits are for SFS and not asynchronous circuit. Refer [6] to know the exact definition of the targeted TRL circuits

. The recent high-density VLSIs also lead to increasing delay faults caused by manufacturing defects, and so manufacturing testing capable of detecting delay faults is also of increasing significance[3], [7]. From these, delay fault testing on TRL circuits is important.

References

References is not available for this document.