1: Introduction
In the recent and future high-density and low-power VLSIs, soft and hard errors frequently occur during system operation. In addition, VLSIs become sensitive to noise and thus it becomes difficult to achieve good signal integrity[1], [2], [3]. So, redundant technologies for improving dependability become increasingly important. Two-rail logic (TRL) circuit design is a well-known class of redundant designs for logic circuits providing strongly fault secure (SFS) property for unidirectional stuck-at faults[4], [5], [6]
Note that the targeted TRL circuits are for SFS and not asynchronous circuit. Refer [6] to know the exact definition of the targeted TRL circuits
. The recent high-density VLSIs also lead to increasing delay faults caused by manufacturing defects, and so manufacturing testing capable of detecting delay faults is also of increasing significance[3], [7]. From these, delay fault testing on TRL circuits is important.