Implications of Total Dose on Single-Event Transient (SET) Pulse Width Measurement Techniques | IEEE Journals & Magazine | IEEE Xplore

Implications of Total Dose on Single-Event Transient (SET) Pulse Width Measurement Techniques


Abstract:

Most pulse width characterization circuits measure single-event transients (SETs) using a target circuit consisting of long inverter chains or temporal latches exposed to...Show More

Abstract:

Most pulse width characterization circuits measure single-event transients (SETs) using a target circuit consisting of long inverter chains or temporal latches exposed to heavy-ions over extended periods of time. For these approaches, circuit-level effects eliminate shorter pulses due to prolonged heavy-ion exposure providing the worst case estimate of measurable transients. Simulation results in the IBM 180 nm and 90 nm technologies corroborate this effect and discuss the resulting factors affecting single event (SE) error cross-sections. Experimental evaluation of such a SET pulse width characterization circuit under heavy-ion exposure showed reduced number of events measured due to total dose effects as expected. Additional experimental and simulation results show that the length of the propagation chains in the target circuit (for capturing SETs), the exposed flux and time (total dose) affect the resulting number of SEs measured.
Published in: IEEE Transactions on Nuclear Science ( Volume: 55, Issue: 6, December 2008)
Page(s): 3336 - 3341
Date of Publication: 19 January 2009

ISSN Information:

References is not available for this document.

I. Introduction

In nanoscale technologies, Single-Event Transients (SETs) dominate the soft-error response of advanced digital CMOS integrated circuits (ICs) [1]–[5]. As a result, it is important to know the SET pulse characteristics (specifically, SET pulse width) to estimate the vulnerability of a given circuit. Various techniques have been used to characterize these SETs, which are temporary perturbations initiated in logic gates. Some of these approaches measure pulse widths directly using on-chip circuits [6], [7] or using off-chip oscilloscopes [8], while others have tried to measure the pulse width indirectly by calculating the cross-section of events generated from such SETs [1], [2]. The type of measurement circuit used decides to a large extent the accuracy achievable.

Select All
1.
J. Benedetto, P. Eaton, K. Avery, D. Mavis, M. Gadlage, T. Turflinger, et al., "Heavy ion induced digital SETs in deep submicron processes", IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3480-3485, Dec. 2004.
2.
P. Eaton, J. Benedetto, D. Mavis, K. Avery, M. Sibley, M. Gadlage, et al., "Single event transient pulse width measurements using a variable temporal latch technique", IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3365-3368, Dec. 2004.
3.
M. J. Gadlage, R. D. Schrimpf, J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Sibley, et al., "Single event transient pulse widths in digital microcircuits", IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3285-3290, Dec. 2004.
4.
P. E. Dodd, M. R. Shaneyfelt, J. A. Felix and J. R. Schwank, "Production and propagation of single-event transients in high-speed digital logic ICs", IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3278-3284, Dec. 2004.
5.
D. G. Mavis and P. H. Eaton, "Soft error rate mitigation techniques for modern microcircuits", Proc. 40th Int. Reliability Physics Symp., pp. 216-225, 2002-Apr.
6.
B. Narasimham, V. Ramachandran, B. L. Bhuva, R. D. Schrimpf, A. F. Witulski, W. T. Holman, et al., "On-chip characterization of single-event transient pulse widths", IEEE Trans. Dev. Mat. Reliab., vol. 6, no. 4, pp. 542-549, Dec. 2006.
7.
Y. Yanagawa, K. Hirose, H. Saito, D. Kobayashi, S. Fukuda, S. Ishii, et al., "Direct measurement of SET pulse widths in 0.2-μm SOI logic cells irradiated by heavy ions", IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3575-3578, Dec. 2006.
8.
V. Ferlet-Cavrois, P. Paillet, D. McMorrow, A. Torres, M. Gaillardin, J. S. Melinger, et al., "Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer SOI devices", IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2104-2113, Dec. 2005.
9.
S. Buchner and M. Baze, "Single-event transients in fast electronic circuits", Proc. IEEE Nuclear Space Radiation Effects Conf. Short Course Text, pp. V-1-V-105, 2001.
10.
T. Calin, M. Nicolaidis and R. Velazco, "Upset hardened memory design for submicron CMOS technology", IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996.
11.
M. J. Gadlage, R. D. Schrimpf, B. Narasimham, B. L. Bhuva, P. H. Eaton and J. M. Benedetto, "Effect of voltage fluctuations on the single event transient response of deep submicron digital circuits", IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2495-2499, Dec. 2007.
12.
M. Nicolaidis, "Time redundancy based soft-error tolerance to rescue nanometer technologies", Proc. VLSI Test Symp., pp. 86-94, 1999-Apr.
13.
B. Narasimham, B. L. Bhuva, W. T. Holman, R. D. Schrimpf, L. W. Massengill, A. F. Witulski, et al., "The effect of negative feedback on single event transient propagation in digital circuits", IEEE Trans. Nucl Sci., vol. 53, no. 6, pp. 3285-3290, Dec. 2006.
14.
[online] Available: http://www.accre.vanderbilt.edu/.
15.
J. D. Black, B. L. Bhuva, M. L. Alles, L. W. Massengill, D. M. Fleetwood, R. D. Schrimpf, et al., "Static and dynamic power comparison of HBD transistor-based circuits designed in a commercial 130 nm technology", Radiation and Its Effects on Components and Systems (RADECS) Conference, 2006.
16.
M. Turowski, A. Raman and R. D. Schrimpf, "Nonuniform total-dose-induced charge distribution in shallow-trench isolation oxides", IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3166-3171, Dec. 2004.
17.
R. C. Lacoe, J. V. Osborn, R. Koga, S. Brown and D. C. Mayer, "Application of hardness-by-design methodology to radiation-tolerant ASIC technologies", IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2334-2341, Dec. 2000.
18.
K. M. Warren, B. D. Sierawski, R. A. Weller, R. A. Reed, M. H. Mendenhall, J. A. Pellish, et al., "Predicting thermal neutron-induced soft errors in static memories using TCAD and physics-based Monte Carlo simulation tools", IEEE Electron Device Lett., vol. 28, pp. 180-182, 2007.
19.
M. J. Gadlage, R. D. Schrimpf, B. Narasimham, J. A. Pellish, K. M. Warren, R. A. Reed, et al., "Assessing alpha particle-induced single event transient vulnerability in a 90 nm CMOS technology", IEEE Electron Device Lett., 2008.

Contact IEEE to Subscribe

References

References is not available for this document.