A Low Memory Design for Hybrid-ARQ Systems

In this paper, we propose a low memory design for Hybrid-ARQ systems that combines the new transmission with previous transmission either with Chase combining (CC) or code combining (IR: incremental redundancy). When the current transmission is decoded in error, the channel inputs to be stored for combining with next transmission are quantized with fewer bits by simply dropping the last few least significant bits (LSB) of the quantization results of current channel inputs. In this way, the proposed method can significantly reduce the memory size while keep the performance loss very small. Both the analytical prediction and the simulation results show that the worst case performance loss can be less than 0.25 dB if we drop half of the quantization bit-width.

I. Introduction

Hybrid-ARQ is a transmission scheme that combines the Forward Error Correction (FEC) and the Automatic Repeat Request (ARQ) for higher transmission reliability and efficiency. It is one of the key techniques in 3G and 4G systems [1]–[4] and is widely applied in most of the new generation wireless systems. For this reason, HARQ is a hot research topic in recent years [5]–[9].