Introduction
One of the key methods to enable transistor gate length scaling over the past several generations has been to scale the gate oxide. This improves the control of the gate electrode over the channel enabling both shorter channel lengths and higher performance. As the gate oxide was scaled the gate leakage increased; this increase in gate leakage was insignificant until the 90nm technology node (Fig. 1). At the 90nm and 65nm nodes, the scaling of the gate oxide slowed as a result of the power limitations from the increase in gate leakage. In order to overcome this at the 45nm technology, a gate dielectric with a higher dielectric constant (high-k) has been introduced. This enabled gate leakage reduction while scaling the gate oxide thickness (Tox) by 0.7x. Trend of inversion Tox and gate leakage vs. technology node (source: Intel)