45nm high-k + metal gate strain-enhanced CMOS transistors | IEEE Conference Publication | IEEE Xplore

45nm high-k + metal gate strain-enhanced CMOS transistors

Publisher: IEEE

Abstract:

At the 45 nm technology node, high-k + metal gate transistors were introduced for the first time on a high-volume manufacturing process [1]. The introduction of a high-k ...View more

Abstract:

At the 45 nm technology node, high-k + metal gate transistors were introduced for the first time on a high-volume manufacturing process [1]. The introduction of a high-k gate dielectric enabled transistors with a 0.7x reduction in Tox (electrical gate oxide thickness) while reducing gate leakage 1000x for the PMOS and 25x for the NMOS transistors. Dual-band edge workfunction metal gates were introduced, eliminating polysilicon gate depletion and providing compatibility with the high-k gate dielectric. High-k + Metal gates have also been shown to have improved variability at the 45 nm node [2]. In addition to the high-k + metal gate, the 35 nm gate length CMOS transistors have been integrated with a third generation of strained silicon and have demonstrated the highest drive currents to date for both NMOS and PMOS. An SRAM cell size of 0.346 mum 2 has been achieved while using 193 nm dry lithography. High yield and reliability has been demonstrated on multiple single, dual-, quad- and six-core microprocessors.
Date of Conference: 21-24 September 2008
Date Added to IEEE Xplore: 17 November 2008
ISBN Information:

ISSN Information:

Publisher: IEEE
Conference Location: San Jose, CA, USA

Introduction

One of the key methods to enable transistor gate length scaling over the past several generations has been to scale the gate oxide. This improves the control of the gate electrode over the channel enabling both shorter channel lengths and higher performance. As the gate oxide was scaled the gate leakage increased; this increase in gate leakage was insignificant until the 90nm technology node (Fig. 1). At the 90nm and 65nm nodes, the scaling of the gate oxide slowed as a result of the power limitations from the increase in gate leakage. In order to overcome this at the 45nm technology, a gate dielectric with a higher dielectric constant (high-k) has been introduced. This enabled gate leakage reduction while scaling the gate oxide thickness (Tox) by 0.7x. Trend of inversion Tox and gate leakage vs. technology node (source: Intel)

References

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