RASP 2.8: A new generation of floating-gate based field programmable analog array

The RASP 2.8 is a very powerful reconfigurable analog computing platform with thirty-two computational analog blocks (CABs). Each CAB has a wide variety of sub-circuits ranging in granularity from multipliers and programmable offset wide linear range Gm blocks to NMOS and PMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating gate transistors. This system exhibits significant performance enhancements over its predecessor in terms of achievable signal bandwidth (> 50 MHz), accuracy (> 9 bits), dynamic range (> 7 decades of current), speed of floating-gate programming (> 200 gates/sec) and isolation between ON and OFF switches. The improved bandwidth is primarily due to an improved routing fabric that includes nearest neighbor connections. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Several complex system examples are presented.

I. RASP 2.8: Overview

The RASP 2.8 FPAA is a powerful system comprising over fifty thousand programmable floating gate elements which can be utilized as programmable interconnect as well as adaptive-computational elements. This leads to a platform capable of performing signal processing and computational tasks beyond a typical digital signal processor but at a fraction of its power. Similar advantages in computation have been demonstrated in [1], but this also marks a paradigm shift in the concept of analog design since its superior performance compared to earlier designs enables this to be used not only as a prototyping tool, but also as an attractive option for the final implementation.