Contents I. Introduction
A TRENCH-GATE MOSFET [1]–[15] is the most preferred power device for medium-to-low-voltage power applications. These are used extensively in control switching, dc–dc converters, automotive electronics, microprocessor power supplies, etc. In all these applications, low on-state resistance is the prime requirement to reduce the conduction power loss and forward voltage drop. Higher drive current, low gate-to-drain capacitance, high transconductance, high breakdown voltage, and inductive switching capability are the other requirements in various applications of power MOSFETs [16]–[20]. Different techniques have been proposed for reducing the on-state resistance and improving other performance parameters [5]–[13], [19]–[22]. Out of various components of the total resistance, the channel resistance is the biggest resistance contributor and needs to be suppressed without significantly affecting the other performance parameters. Among the techniques of reducing channel resistance, the use of channel has been reported to give up to 10% improvement in the on-resistance [8]. The strained-Si channel is also used to significantly improve current drivability and transconductance in lateral power MOSFETs [20], [21]. However, the same is not feasible in a conventional trench structure as the formation of strained-Si channel results in the elimination of the accumulation region, reducing its damage immunity for inductive load switching, which is also an essential requirement in some applications [9]. Therefore, the main objective of this brief is to propose an improved trench-gate MOSFET structure that offers lower on-resistance by allowing the formation of strained-Si channel and efficient confinement of the carriers near the trench sidewalls in the accumulation layer needed for improved inductive switching capability.
