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A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology | IEEE Journals & Magazine | IEEE Xplore

A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology


Abstract:

This paper presents a second-order delta-sigma (/spl Delta//spl Sigma/) modulator fabricated in a 70 GHz (f/sub T/), 90 GHz (f/sub max/) AlInAs-GaInAs heterojunction bipo...Show More

Abstract:

This paper presents a second-order delta-sigma (/spl Delta//spl Sigma/) modulator fabricated in a 70 GHz (f/sub T/), 90 GHz (f/sub max/) AlInAs-GaInAs heterojunction bipolar transistor (HBT) process on InP substrates. The modulator is a continuous time, fully differential circuit operated from /spl plusmn/5 volt supplies and dissipates 1 W. At a sample rate of 3.2 GHz and a signal bandwidth of 50 MHz (OSR=32100 MSPS Nyquist rate) the modulator demonstrates a Spur Free Dynamic Range (SFDR) of 71 dB (12-b dynamic range). The modulator achieves the ideal signal-to-noise ratio (SNR) of 55 dB for a second-order modulator at an oversampling ratio (OSR) of 32. The design of a digital decimation filter for this modulator is complete and the filter is currently in fabrication in the same technology. This work demonstrates the first /spl Delta//spl Sigma/ modulator in III-V technology with ideal performance and provides the foundation for extending the use of /spl Delta//spl Sigma/ modulator analog-to-digital converters (ADC's) to radio frequencies (RF).<>
Published in: IEEE Journal of Solid-State Circuits ( Volume: 30, Issue: 10, October 1995)
Page(s): 1119 - 1127
Date of Publication: 06 August 2002

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