1 Introduction
In order to fabricate low-power and high-performance CMOS LSI with scaled dimensions, thickness reduction of gate dielectrics is one of the important challenges. Conventional SiO2 or gate dielectrics are facing severe gate leakage current problem due to direct tunneling and thus the thickness scaling is almost approaching to physical limit. Therefore, the use of high dielectric constant (high-k) material is strongly required. Among various high-k materials, Hf-based materials such as HfSiON and HfO2 are thought to be the most promising for hp65 node [1]–[4]. Application of this material to further scaled devices such as hp45 node and beyond is the most straightforward from the fabrication point of view. According to the ITRS roadmap [5], electrical equivalent oxide thickness (EOT) for the hp45 and hp32 nodes should be reduced to 0.9nm and 0.8nm respectively for low operating power (LOP) devices. In this report, we will discuss the scalability of Hf-based high-k materials and point out that these materials will be used in hp45 node and beyond.