Abstract:
In this work, we implemented the robust evolutionary controlled (REC) filter in a FPGA platform. Due unknown a priori statistical information, we replace the Optimal Wien...Show MoreMetadata
Abstract:
In this work, we implemented the robust evolutionary controlled (REC) filter in a FPGA platform. Due unknown a priori statistical information, we replace the Optimal Wiener Filter by its rough approximation referred to as REC filter. The evolution of the filter is controlled by changing/choosing the vector of the controlled parameters γ. Such a control provides additional degrees of freedom of the filter. We report and discuss some implementation results in the Xilinx Virtex-II Pro XC2VP30 FPGA related to enhancement of the uncertain real-world RS imagery, these are indicative of the significantly increased performance efficiency gained with the developed approach.
Date of Conference: 28-30 April 2008
Date Added to IEEE Xplore: 13 June 2008
ISBN Information: