Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric Structure

A universal compact potential model for all types of double-gate MOSFETs is presented. An analytical closed-form solution to a 2D Poisson's equation is obtained with the approximation that a vertical channel potential distribution is a cubic function of position. As a result, an analytical equation for the threshold voltage is derived from the proposed potential model. Different gate work functions and independent gate biases for front and back gates are considered, and the proposed model is found to be valid for an arbitrary double-gate structure: a symmetric versus asymmetric double gate and a tied versus separated double-gate structure. The threshold voltage behaviors for double-gate MOSFETs are investigated for various device dimensions. The back-gate effects of the separated double gate are also investigated for various silicon channel thicknesses and gate oxide thicknesses. Last, a process-induced threshold voltage fluctuation is estimated for symmetric and asymmetric separated double-gate MOSFETs. The analytical solution of the threshold voltages is verified by a comparison with simulation results in terms of the gate length, the silicon thickness, and the gate oxide thickness. A good agreement between two sets of results is obtained.

I. Introduction

Two-dimensional channel potential distributions for MOSFETs have been widely investigated in efforts to elucidate the device characteristics, such as the threshold voltage, the subthreshold swing, and the drain-induced barrier lowering [1]–[7]. Obtaining a closed form of potential distribution models is crucial to evaluate the device characteristics depending on device and process parameters. From the closed form, a guideline for device scalability, referred to as “scaling theory,” was proposed [2], [3], [6]. According to the scaling theory, short-channel effects could be optimized if the minimum gate length satisfied the condition of , where is the gate length, is a constant, and is the characteristic length. Since is a function of device parameters such as the dielectric constant of oxide , oxide thickness , and junction depth (or the body thickness for ultrathin body MOSFETs), tolerable device dimensions (, , or ) can be fixed with given . To obtain a comprehensive understanding of a potential distribution, it is important to evaluate short-channel effects as well as device scalability.