1. Introduction
VLSI circuits are being aggressively scaled to increase functionality and performance with reduced cost and power dissipation. This aggressive scaling has introduced serious problems for the semiconductor industry [1] [2]. The performance of deep-submicron integrated circuits is increasingly dominated by the interconnects performance [1] [2]. Continuous scaling is reducing gate delays, but unfortunately, is rapidly increasing interconnect delays. The International Technology Roadmap for Semiconductors ITRS predicted that the performance improvement is likely to begin to saturate unless a paradigm shift from present integrated circuits architecture is introduced [1] [2].