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Analytical Model for the Propagation Delay of Through Silicon Vias | IEEE Conference Publication | IEEE Xplore

Analytical Model for the Propagation Delay of Through Silicon Vias


Abstract:

This paper explores the modeling of the propagation delay of through silicon vias (TSVs) in 3D integrated circuits. The electrical characteristics and models of the TSVs ...Show More

Abstract:

This paper explores the modeling of the propagation delay of through silicon vias (TSVs) in 3D integrated circuits. The electrical characteristics and models of the TSVs are very crucial in enabling the analysis and CAD in 3D integrated circuits. In this paper, an analytical model for the propagation delay of the TSV as a function of its physical dimensions is proposed. The presented analytical model is in great agreement with simulations using electromagnetic field solver and lossy transmission line circuit model. Compared to earlier interconnect models, the presented analytical model provides higher accuracy and fidelity in addition to its simplicity. Hence, the presented analytical model is very useful in the analysis of 3D integrated circuits.
Date of Conference: 17-19 March 2008
Date Added to IEEE Xplore: 31 March 2008
Print ISBN:978-0-7695-3117-5

ISSN Information:

Conference Location: San Jose, CA, USA

1. Introduction

VLSI circuits are being aggressively scaled to increase functionality and performance with reduced cost and power dissipation. This aggressive scaling has introduced serious problems for the semiconductor industry [1] [2]. The performance of deep-submicron integrated circuits is increasingly dominated by the interconnects performance [1] [2]. Continuous scaling is reducing gate delays, but unfortunately, is rapidly increasing interconnect delays. The International Technology Roadmap for Semiconductors ITRS predicted that the performance improvement is likely to begin to saturate unless a paradigm shift from present integrated circuits architecture is introduced [1] [2].

References

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