Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit design. In this study, we present a fully digital on-chip reliability monitor for high-resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators, one stressed and the other unstressed, to achieve 50 X higher delay sensing resolution than that of prior techniques. The differential frequency measurement technique also eliminates the effect of common-mode environmental variation such as temperature drifts between each sampling points. A 265 X 132 mum²test chip implementing this design has been fabricated in a 1.2 V, 130 nm CMOS technology. The measured resolution of the proposed monitoring circuit was 0.02%, as the ring oscillator in this design has a period of 4 ns; this translates to a temporal resolution of 0.8 ps. The 2 mus measurement time was sufficiently short to suppress the unwanted recovery effect from concealing the actual circuit degradation.

I. Introduction

As CMOS process technology continues to follow an aggressive scaling roadmap, designing reliable circuits has become ever more challenging with each technology node. Reliability issues such as bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) has become more prevalent as the electrical field continues to increase in nanoscale CMOS devices. One of the most pressing of these challenges is negative bias temperature instability (NBTI) [1]–[4] caused by the trap generation in the Si–SiO₂ interface of pMOS transistors (Fig. 1). Structural mismatch at the Si-SiO₂ interface causes dangling bonds, which act as interfacial traps. During the hydrogen passivation process that follows oxidation, dangling Si bonds are transformed into Si-H bonds. These bonds are weak enough to break during device operation, causing H atoms to diffuse into gate oxide, and the broken bonds that remain become traps, effectively degrading the drive current of pMOS transistors. NBTI is characterized by a positive shift in the absolute value of the pMOS threshold voltage , which occurs when the device is stressed , and this effect is more pronounced at high temperatures. This degradation in has believed to exhibit a power-law dependency on time and is an exponential function of the stress voltage level as well as temperature. When the stress conditions are removed (i.e., ), the device enters a recovery or passivation phase, where H atoms diffuse back towards the Si–SiO₂ interface and anneal the broken Si–H bonds, thereby reducing [Fig. 1(b) and (c)] [5]–[11]. Fig. 1.

Cross section of pMOS device under (a) NBTI stress and in (b) recovery mode. (c) pMOS Vt degradation for alternating stress and recovery periods in 130 nm CMOS [5].