Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip

The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space _* Power) ]. It doubles the throughput performance and performance/watt, and provides >10times improvement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a floating point and graphics unit and an advanced cryptographic unit which provides high enough bandwidth to run the two 10 Gb Ethernet ports encrypted at wire speeds. There is a 4 MB Level2 cache on chip. Each of the four on-chip memory controllers controls two FBDIMM channels. Niagara2 has 503 million transistors on a 342 mm² die packaged in a flip-chip glass ceramic package with 1831 pins. The chip is built in Texas Instruments' 65 nm 11LM triple-Vt CMOS process. It operates at 1.4 GHz at 1.1 V and consumes 84 W.

I. Introduction

Today's datacenters face extreme throughput, space, and power challenges. Throughput demands continue increasing while space and power are fixed. The increase in power consumed by the servers and the cost of cooling has caused a rapid increase in the cost of operating a datacenter. The Niagara1 processor [5] (also known as the UltraSPARC T1) made a substantial attempt at solving this problem. This paper describes the implementation of the Niagara2 processor, designed with a wide range of applications in mind, including database, web-tear, floating-point, and secure applications. Niagara2, as the name suggests, is the follow-on to the Niagara1 processor based on the CMT architecture optimized for SWaP.