A 470-μw multi-modulus injection-locked frequency divider with division ratio of 2, 3, 4, 5 and 6 in 0.13-μm CMOS

This paper presents a multi-modulus injectionlocked frequency divider (ILFD) based on a ring oscillator using inverter chains for a small area and low power consumption. In the proposed ILFD, division ratio of 2, 3, 4, 5 and 6 can be performed by selecting a specific loop which consists of a transmission gate and several delay cells. A prototype chip implemented in 0.13 μm CMOS process operates at 5 GHz while consuming 470 μW from 1.2 V supply, where 350 μW is dissipated in the core of the ILFD. The proposed ILFD is the first reported multi-modulus ILFD with a digitally controlled division ratio and the size of the ILFD is 44 × 33 μm². This number is one of the smallest area that have been reported for a ILFD.

I. Introduction

Due to the explosive growth of low-cost wireless hand-held devices, power consumption has become one of the most important design criteria in wireless transceivers. A frequency synthesizer in wireless transceivers occupies a significant portion of total power consumption. Since most of the power are consumed by an VCO and a frequency divider in the frequency synthesizer, it is necessary to design low power VCO and frequency divider for a low power frequency synthesizer.