Modelling of Dual-Gate MOSFET 1/f Noise in Linear Region

This paper presents experimental and numerical results for the dual-gate MOSFET (DGMOSFET) normalized 1/f noise parameter B/I_D ² in linear working region. In modelling, gate-to-gate interelectrode space influence is taken into account with the fitting parameter m, which is defined as the ratio of inner transistors channel lengths. Model and methodology for the normalized 1/f noise parameter calculation for the DGMOSFET linear region have been proposed. The model is based on the ac current approach in the DGMOSFET low-frequency small-signal noise equivalent circuit and carrier-number fluctuations and correlated mobility fluctuations. It has been shown that discrepancy between measured data and numerical results obtained only by the DeltaN model can be explained by use of the gradual channel approximation MOSFET model and the unified 1/f noise model.

I. Introduction

Continuous scaling of MOSFETs to the sub-micron range has considerably increased the performance of integrated circuits. Some of the results of miniaturisation are higher level of integration in the digital CMOS technology, implementation of the mixed mode (analogue/digital) circuits on the same chip, MOS implementation in analogue RF circuits, applications where a dual-gate MOSFET (DGMOSFET) is of interest. In order to fully understand the potential of new MOSFET circuits with DGMOSFETs in analogue and mixed-mode applications, limitations arising from noise must be examined. Generally, noise determines fundamental limits on circuit performance and plays a significant role in analogue circuit design. Moreover, noise increases oscillator phase noise in RF applications [1] and the DC offset level in the baseband part of wireless applications. Therefore, in order to optimize noise performance in up-to-date applications, noise models that describe experimental behaviour well, are required.