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Online Protocol Testing for FPGA Based Fault Tolerant Systems | IEEE Conference Publication | IEEE Xplore

Online Protocol Testing for FPGA Based Fault Tolerant Systems


Abstract:

In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategie...Show More

Abstract:

In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be performed - in the paper the lowest level is presented. The definition of dedicated language for the description of possible communication faults is presented. The core generator is used to produce VHDL code describing the behaviour of the checker.
Date of Conference: 29-31 August 2007
Date Added to IEEE Xplore: 08 October 2007
ISBN Information:
Conference Location: Lubeck, Germany

I. Instructions

Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight. Reconfigurable systems implemented using user-programmable logic elements such as FPGA are well suited for applications where high dependability is required. The problems combined with the design of dependable systems include error detection during system operation, fast fault location, quick recovery from temporary failures, and fast permanent-fault repair [4].

References

References is not available for this document.