LADT Arithmetic Improved and Hardware Implemented for FPGA -Based ECG Data Compression

To resolve the problem of complex operation of the linear approximation distance threshold (LADT) algorithm, some improved researches were made to the algorithm by taking the characteristic of electrocardiograph (ECG) signal and the advantages of field programmable gate arrays (FPGA) into account. The paper puts forward a real time compression method with much less mathematical operation and much easier real-time implementation. With the artificial and experimental verification, it turned to be that the arithmetic has the advantages of low distortion and in real time. In the application of improved fast LADT algorithm, the paper designed the hardware system of ECG data compression based on FPGA and the program of the algorithm based on very high speed integrated circuit hardware description language (VHDL). And the experiment results of this system turned to be good performance. The approach can be easily extended to other similar applications.

I. Introduction

The development of efficient real-time compression methods for ECG data transmission in limited bandwidth wireless networks such as the General Packet Radio Service (GPRS) systems is crucial for a wider use of such wireless telemetrically services in healthcare systems. It is well know that in order to use the available network bandwidth in an efficient way, a compression algorithm is required. In the last decade, many ECG data compression algorithms have been presented [1] [4]. Nevertheless, most of these studies direct their efforts in store and forward compression, leaving real-time operation as a possible future application without giving any specific result in this area. Although in [4] a real time ECG compression based on the wavelet transform is described, the compression algorithm was realized on PC and the programming language used for the compression was C. To the authors knowledge no study is reported yet on fast ECG compression and hardware implementation.