Pseudo Real-Time System for Visualisation of 3D Scenes

A novel pseudo real-time 3D visualisation system is proposed in this paper. The proposed system has been developed using the TI (Texas instruments) DM642 EVM board which is a standalone digital media processing board. The system also includes a stereo video capture module consisting of two PAL cameras and a 3D display unit for visualisation of 3D video input. The core algorithm utilises images captured from the cameras and generates 6 virtual in between views using interpolation techniques. The combined views (eight views of 2D images) are displayed on the 3D monitor using a proprietary method developed specifically for X3D monitors. The advantage of the proposed system is that real 3D impressions are able to be visualised in front of the 3D monitor in pseudo real-time without any special glasses. The proposed system has been evaluated on a number of real scenes. The limitations of our system will be discussed and the corresponding solutions will be given at the end of this paper.

1. Introduction

A novel pseudo real-time 3D visualisation system is proposed in this paper. Figure 1 illustrates the hardware configuration of the system that consists of a core section, a capture section and a display section. The core section is the TI DM642 EVM board which is a standalone development platform. Its processor is the TMS320DM642 operating at 720 MHz. This processor is a fixed-point digital media processor and optimised for video and image applications. This implies that fixed-point calculations are able to take advantage of the processor's architecture for code optimisation, such as software pipelining (the TMS320DM642 has 256-bit address bus, and up to eight 32-bit instructions can be executed in one cycle). The TMS320DM642 has 32 KB Level 1 cache (16 KB Level 1 Program cache (L1P), 16 KB Level 1 Data cache (L1D)) and 256 KB Level 2 cache (L2) which can be used as a cache, SRAM or mixed cache and SRAM. The TI DM642 EVM board has 32 MB synchronous DRAM, which is accessed externally from the processor's point of view [6]. This is large enough to meet the memory requirements in our application.