A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems

We present a 32 times 32 pixels contrast retina microchip that provides its output as an address event representation (AER) stream. Spatial contrast is computed as the ratio between pixel photocurrent and a local average between neighboring pixels obtained with a diffuser network. This current-based computation produces an important amount of mismatch between neighboring pixels, because the currents can be as low as a few pico-amperes. Consequently, a compact calibration circuitry has been included to trimm each pixel. Measurements show a reduction in mismatch standard deviation from 57% to 6.6% (indoor light). The paper describes the design of the pixel with its spatial contrast computation and calibration sections. About one third of pixel area is used for a 5-bit calibration circuit. Area of pixel is 58 mum times 56 mum , while its current consumption is about 20 nA at 1-kHz event rate. Extensive experimental results are provided for a prototype fabricated in a standard 0.35-mum CMOS process.

I. Introduction

Traditional CMOS imagers operate under a frame-based philosophy. That is, the image information (intensity, contrast,) of each pixel is sequentially scanned out with a constant periodicity. After a complete period, the whole image has been read. For consumer video systems, the whole image is usually scanned out in a 20–30-ms period. This restriction becomes a problem when image resolution increases, as the time allocated to read each pixel decreases. The problem of this scanning approach is that the communication bandwidth is equally allocated for each pixel regardless of its relevance. Thus, communication bandwidth (and power) is wasted on nonrelevant or little relevant pixels.