Maximum frequency of operation of CMOS Static Frequency dividers: Theory and Design techniques | IEEE Conference Publication | IEEE Xplore

Maximum frequency of operation of CMOS Static Frequency dividers: Theory and Design techniques


Abstract:

This paper presents a theoretical analysis of the maximum frequency of operation of CMOS static frequency dividers. The approach is based on the transient analysis of out...Show More

Abstract:

This paper presents a theoretical analysis of the maximum frequency of operation of CMOS static frequency dividers. The approach is based on the transient analysis of output voltages derived from differential equations of the large-signal model of the circuit. Tradeoffs and design techniques for very high frequency dividers have been discussed on the basis of the derived expression. An inductor-less 45 GHz divider and a shunt-peaked 60 GHz divider have been designed in 0.13 μm process following the suggested design techniques. Detailed simulation results have been presented.
Date of Conference: 10-13 December 2006
Date Added to IEEE Xplore: 02 July 2007
ISBN Information:
Conference Location: Nice, France

I. Introduction

Frequency divider is a fundamental block in wireless systems, its applications ranging from frequency synthesis to clock recovery in high-speed serial links. With the increasing demand for high speed data rate in the range of 40 to 60 for wireless applications, design of broadband frequency divider has become a critical issue as they often turn out to be the bottleneck in monolithic integration due to their high power consumption [1]. Analog implementations like regenerative and injection-locking dividers can provide low power solutions for very high frequencies [3], [4] but they are inherently narrow-band. Static frequency dividers are wideband dividers which have been popularly realized using HBT technology reaching an operating frequency of near 100 GHz [2], [5], [6]. CMOS frequency dividers have come up recently, however at a lower speed. One of the fastest static CMOS frequency divider reported [7] has been at 33 GHz consuming 22 per MS-FF.

References

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