I. Introduction
Frequency divider is a fundamental block in wireless systems, its applications ranging from frequency synthesis to clock recovery in high-speed serial links. With the increasing demand for high speed data rate in the range of 40 to 60 for wireless applications, design of broadband frequency divider has become a critical issue as they often turn out to be the bottleneck in monolithic integration due to their high power consumption [1]. Analog implementations like regenerative and injection-locking dividers can provide low power solutions for very high frequencies [3], [4] but they are inherently narrow-band. Static frequency dividers are wideband dividers which have been popularly realized using HBT technology reaching an operating frequency of near 100 GHz [2], [5], [6]. CMOS frequency dividers have come up recently, however at a lower speed. One of the fastest static CMOS frequency divider reported [7] has been at 33 GHz consuming 22 per MS-FF.