Contents The development of multimedia communications has demanded for multi-Gb/s data-transmission systems. Such systems require high-speed front-end amplifiers in the receive paths. The amplifiers must deal with tiny input signals, providing output signals as large as hundreds of millivolts for the subsequent clock and data recovery. In this paper, the design and experimental verification of a 40Gb/s transimpedance-AGC (TIA-AGC) amplifier realized in 90nm CMOS technology are described.
Abstract:
A 40Gb/s transimpedance-AGC amplifier is implemented in 90nm CMOS. The TIA uses reversed triple-resonance networks and negative feedback in a common-gate configuration. O...Show MoreMetadata
Abstract:
A 40Gb/s transimpedance-AGC amplifier is implemented in 90nm CMOS. The TIA uses reversed triple-resonance networks and negative feedback in a common-gate configuration. Operating at 40Gb/s, the amplifier provides 520 mVpp-diff output swing for a current range of 0.44 to 4 mApp, achieved by AGC. The integrated input-referred noise is 3.6μArms and the total power consumption is 75mW.
Date of Conference: 11-15 February 2007
Date Added to IEEE Xplore: 18 June 2007
ISBN Information:
