Field Programmable Gate Array (FPGA) Based Neural Network Implementation of Stator Flux Oriented Vector Control of Induction Motor Drive

In this work, it is proposed the implementation of the SFOVC-ANN using field programmable gate array (FPGA). The proposed scheme assure parallel processing of the ANN, since the circuit design was done in such way that the neurons in the same layer processes the input signals in parallel. The non-linear sigmoidal transfer function is implemented using Spline Interpolation, which guarantees an excellent precision. Initially in the digest, a description of the proposed system is given. Then, the nonlinear neuron implementation strategy is explained. Following this, the FPGA implementation of ANN is described. Finally, simulation and experimental results are given to substantiate the development.

I. Introduction

Neural network based stator flux oriented vector control (SFOVC-ANN) of induction motor drive has been a very popular research topic in the recent literature. The main motivation of this research originated with the objective of integrating intelligent control with the high performance drive control. The stator flux oriented vector control has the advantage that it is less parameter dependent, i.e., it is dependent on machine stator resistance (Rs) only which can be compensated easily. However, the disadvantage is that the control is more complex because of the decoupling compensation required in the flux control loop. Normally, digital signal processor (DSP) is used to implement the control strategy. However, neural network based intelligent control provides the advantages of fast parallel signal processing, economical ASIC chip implementation, adaptability, and inherent fault tolerance capability. The design, analysis and simulation study of neural network based stator flux oriented vector control has been widely published in the literature, However, practical implementation of ANN-based intelligent control is yet an open research topic. Traditionally, ANN has been implemented by a single or multiple DSPs. The DSP technology has advanced tremendously in the recent years. However, the main disadvantage with DSP implementation is sluggishness due to sequential computation. of course, multiple DSPs can alleviate this problem at the expense of high high cost. The ASIC chip implementation, on the other hand, can be economical provides the advantage of parallel signal processing. A custom neural ASIC chip is expensive with long development cycle. However, ANN implementation by field programmable gate array (FPGA) has the advantages of flexibility and cost effectiveness, besides the high execution speed. It is very convenient for laboratory implementation of a project. Therefore, FPGA-based ANN implementation has been widely reported in the literature. In this project, FPGA has been used to implement the SFOVC-ANN (see Fig. 1). Initially in the digest, a description of the proposed system is given. Then, nonlinear neuron implementation strategy is explained. Following this, the FPGA implementation of ANN is described. Finally, simulation and experimental results are given to substantiate the development.