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A New Design for 7:2 Compressors | IEEE Conference Publication | IEEE Xplore

Abstract:

High order compressors play a specific role in realizing high speed multipliers. By increasing the demand for fast multiplication process, high order compressors have att...View more

Abstract:

High order compressors play a specific role in realizing high speed multipliers. By increasing the demand for fast multiplication process, high order compressors have attracted many researchers to this field. In this paper a new implementation for 7:2 compressors, based on the conventional architecture, is proposed. According to the results, the design presented achieves a remarkable improvement in terms of speed (especially in low voltages) and power consumption over the best counterpart. This accomplishment is the direct result of shortening the critical delay path in the proposed circuit design. As the simulation results demonstrate, the structure presented here has improved the power consumption from minimum 0.07% (at supply voltage = 3.5 volt) through maximum 11% (at 1.2 volt), and the speed of the circuit from minimum 19% (at 3.5 volt) through maximum 23% (at 1.2 volt). HSPICE is the circuit simulator used, and the technology being used for simulations is 0.25 mum technology.
Date of Conference: 13-16 May 2007
Date Added to IEEE Xplore: 11 June 2007
ISBN Information:

ISSN Information:

Publisher: IEEE
Conference Location: Amman, Jordan

1. Introduction

The speed of multipliers is a critical issue in determining the performance of microprocessors. Microprocessors use multipliers within their arithmetic logic units, and digital signal processing systems require multipliers to implement DSP algorithms such as convolution and filtering. The demand for high-speed multipliers is continuously increasing. The fast multiplication process consists of 3 steps: partial product generation, partial product reduction and final carry-propagating addition. Various recoding schemes are used to reduce the number of partial products. Compressors have been widely used for reduction process which usually contributes the most to the delay, power and area of the multiplier. To achieve a better performance, the use of higher order compressors instead of conventional compressors, e.g. 3:2 compressors, have been considered. The reduction process finally results in a 2-row matrix, and then a high speed adder is used to get the final result from the two rows [4]–[13].

References

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