1. Introduction
The speed of multipliers is a critical issue in determining the performance of microprocessors. Microprocessors use multipliers within their arithmetic logic units, and digital signal processing systems require multipliers to implement DSP algorithms such as convolution and filtering. The demand for high-speed multipliers is continuously increasing. The fast multiplication process consists of 3 steps: partial product generation, partial product reduction and final carry-propagating addition. Various recoding schemes are used to reduce the number of partial products. Compressors have been widely used for reduction process which usually contributes the most to the delay, power and area of the multiplier. To achieve a better performance, the use of higher order compressors instead of conventional compressors, e.g. 3:2 compressors, have been considered. The reduction process finally results in a 2-row matrix, and then a high speed adder is used to get the final result from the two rows [4]–[13].