Dynamic Voltage Scaling Algorithms for Power Constrained Motion Estimation

In this paper, we apply dynamic voltage scaling (DVS) to the matching metric computation (MMC) used within motion estimation (ME) in typical video encoders. Our approach is based on "soft DSP" concepts. We analyze the effect of ME errors (due to DVS) in overall coding performance. We propose a model for the resulting rate increase (at a given fixed quantization parameter) as a function of input characteristics and input voltage, for given ME algorithm and MMC architecture. This model is validated using simulations. We then compare ME algorithms and MMC architectures, and propose a method for power saving of the ME process that depend on input characteristics and desired coding performance. As an illustration of the potential benefits of allowing computation errors, we show that allowing errors that lead to a small rate increase (about 3%) produces 37% power savings in the ME process, as compared to not using DVS. An essentially "error-free" DVS approach (no rate penalty) can achieve around 10% power savings.

1 INTRODUCTION

Power (or energy) is the most important design constraint in many VLSI design scenarios [11]. Many approaches have been proposed for power constrained VLSI, ranging from circuit level to architectural and algorithmic level [7], [9]. Dynamic voltage scaling (DVS) is an attractive technique to reduce power consumption, as lowering input voltage by a factor , reduces energy dissipation by almost a factor [9]. Soft DSP is an efficient approach for DVS [9] that has been applied to low level systems, such as adders and multiplier-accumulators (MACs) often used in signal processing applications (e.g., linear filters and multi-input-multi-output, MIMO, systems). In soft DSP systems the input voltage is below critical voltage (i.e., we have voltage over scaling, VOS) which leads to input-dependent soft errors. Then, soft-error tolerance is achieved by using explicit error control blocks that provide error concealment so as to operate with negligible loss in algorithm performance.