Sensitivity Controllable CMOS Image Sensor Pixel Using Control Gate Overlaid on Photodiode

A new sensitivity controllable pixel structure is proposed for CMOS active-pixel image sensor. The proposed pixel structure has a sensitivity control gate overlaid on the photodiode. The sensitivity of the pixel is controlled by the bias voltage of the control gate that forms a variable accumulation-mode MOS capacitor. The prototype sensor is fabricated with a 0.35-mum CMOS process and consists of 60 times 240 pixels with 5.6-mum pixel pitch. Measurement results show that the sensitivity of the photodiode can be controlled by a factor of 4.

I. Introduction

CMOS active-pixel image sensors (APS) have many advantages over charge-coupled device (CCD) image sensor including low-voltage operation, less power consumption, and camera-on-chip integration [1]. In particular, the pixel-level signal processing ability of CMOS APS is much greater than that of CCD [2]. Generally, in CMOS APS, the sensitivity of the individual pixel cannot be changed once it is determined by the photodetector structure, but many pixel-level signal processing applications such as silicon retina, smart image sensors, and wide dynamic range sensors require the pixel-level sensitivity control [3]–[7]. However, previously reported sensitivity controllable pixels have drawbacks such as large pixel area [3]–[6], small signal swing [6], or large fixed pattern noise (FPN) [5]–[7].