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Coupling-aware Dummy Metal Insertion for Lithography | IEEE Conference Publication | IEEE Xplore

Coupling-aware Dummy Metal Insertion for Lithography


Abstract:

As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufact...Show More

Abstract:

As integrated circuits manufacturing technology is advancing into 65nm and 45nm nodes, extensive resolution enhancement techniques (RETs) are needed to correctly manufacture a chip design. The widely used RET called off-axis illumination (OAI) introduces forbidden pitches which lead to very complex design rules. It has been observed that imposing uniformity on layout designs can substantially improve printability under OAI. For metal layers, uniformity can be achieved simply by inserting dummy metal wire segments at all free spaces. Simulation results indeed show significant improvement in printability with such a dummy metal insertion approach. To minimize mask cost, it is advantageous to use dummy metal segments that are of the same size as regular metal wires due to their simple geometry. But these dummy wires are printable and hence increase coupling capacitances and potentially affect yield. The alternative is to use a set of parallel sub-resolution thin wires (which is not printed) to replace a printable dummy wire segment. These invisible dummy metal segments do not increase coupling capacitances but bring a higher lithography cost, which includes mask cost and RET/process expense. This paper presents a strategy for dummy metal insertion that can optimally trade off lithography cost and coupling capacitance. In particular, we present an optimal algorithm that can minimize lithography cost subject to any given coupling capacitance bound. Moreover, this dummy metal insertion achieves a highly uniform density because of the locality of coupling capacitance, which automatically ameliorates chemical mechanical polish (CMP) problem.
Date of Conference: 23-26 January 2007
Date Added to IEEE Xplore: 07 May 2007
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ISSN Information:

Conference Location: Yokohama, Japan

I. Introduction

The continuing CMOS technology scaling down has pushed the integrated circuits manufacturing to a limit. Photolithography becomes a main issue related to process variations and yield problems. Resolution enhancement techniques (RETs) have been used extensively for improvement. Optical proximity correction (OPC) is widely used to get the desired features. Modified illuminations, such as off-axis illumination (OAI), are implemented to improve quality of certain features.

References

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