I. Introduction
As CMOS technologies are scaling to the 45-nm regime and beyond, undoped (or lightly doped) double-gate (DG) MOSFETs have become the most promising candidates for extending the device-scaling roadmap because of a number of advantages such as ideal 60-mV/decade subthreshold slope, free-dopant-associated fluctuation effects, excellent short-channel-effect (SCE) immunity, and unique mobility enhancement [1]–[5]. To allow large-scale evaluation of the performance of DG-MOSFETs, a compact model is needed. Modeling of DG-MOSFETs requires a different approach compared with conventional bulk CMOS due to several unique physical effects of the DG-MOSFETs, such as the two conducting-interface coupling, volume inversion, and the carrier energy-level quantization [6]–[15]. Recently, extensive study of DG-MOSFET device physics and transport mechanism has been performed [6]–[10] and some preliminary core models have also been proposed [11]–[21]. For example, two research groups solved the 1-D Poisson equation to derive analytical solutions for the potential, charge, and current–voltage characteristics [9]–[18]. Other groups used the charge-based approach and focus on analytical charge and current expressions [19]–[21].