Real Time FPGA-based Architecture for Video Applications

Motion estimation constitutes a significant computational part of video compression standards such as MPEG4. The most frequently used technique is based on a full search block matching algorithm which is highly computing intensive and requires a large number of I/O pins and large bandwidth to obtain real-time performance. This paper describes an efficient reconfigurable architecture suitable for motion estimation with minimum latency and maximum throughput, based on a systolic array. The architecture comprises a smart memory schema to reduce the number of access to data memory and router elements to handle processing blocks interconnection. Every PE in the array includes a double ALU in order to search multiple macro-blocks in parallel. The functionality has been extended to support operations involved in some other low-level algorithms. Preliminary results show that a peak performance in the order of GOPS can be achieved

1. Introduction

Motion estimation is a key technique in most algorithms for video compression that exploits the spatial and temporal redundancies present in a digital video sequence [1]. Nevertheless, it is also the most computationally intensive task, involving up to 65% of the total computational resources of the video coder and requiring high power, throughput and memory utilization [2], which justifies the great research effort that has been made to develop efficient dedicated architectures and specialized processors.