An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation

Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and research, multiple core processor simulation environments are necessary. A well-known positive feedback property of computer design is that we use today's computers to design tomorrow's. Thus, with the emergence of chip multiprocessors, it is natural to re-examine simulation environments written to exploit parallelism. In this paper we present a programming methodology for directly converting existing uniprocessor simulators into parallelized multiple-core simulators. Our method not only takes significantly less development effort compared to some prior used programming techniques, but also possesses advantages by retaining a modular and comprehensible programming structure. We demonstrate our case with actual developed products after applying this method to two different simulators, one developed from IBM Ibrandot and the other from the SimpleScalar tool set. Our SimpleScalar-based framework achieves a parallel speedup of 2.2times on a dual-CPU dual-core (4-way) Opteron server

I. Introduction

High-level simulation has been a primary means of design and planning for all modern uniprocessor and multiple-core processor designs. Although many multicore simulators exist today, questions remain regarding how to best develop these simulators to take advantage of existing platforms. Computer design is one of the few fields with a positive feedback property, of designing tomorrow's computers using today's. In order to best utilize multithreaded and multicore processors, these simulators should make use of parallelism.