A 0.1-$\mu{\hbox {m}}$ 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal times2 write and can be increased to ~2.67 MB/s with times16 write. Endurance and retention characteristics are measured to be 10⁷ cycles and ten years at 99 degC

I. Introduction

Ongoing progress in phase-change random access memory (PRAM) technology since early 2000 has confirmed its great potential as a next-generation high-density nonvolatile memory [1]–[5]. Besides the simple cell structure with superior scalability [6], one of the most fundamental advantages of PRAM over the existing nonvolatile memories is its write performance. For example, Flash memory, which is used primarily in mass storage applications, undergoes some inherent restrictions from which PRAM does not have to suffer. In Flash memory, since old data cannot be overwritten by new data, the entire block has to be frequently erased before programming new data, conflicting with its relatively low program/erase endurance limit. This requires sophisticated data handling algorithms, like garbage-collection and wear-leveling. In this paper, a 256-Mb PRAM implemented in 0.1- CMOS technology, featuring 66-MHz burst-read operation, is presented. To supply sufficient write current from the write-driver to the accessed cell and evaluate write-throughput characteristics under the low supply voltage (1.8 V), a particular parallel organization of charge-pump units is utilized. Fig. 1.

Chip architecture for 256-Mb PRAM.