Abstract:
A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were devel...Show MoreMetadata
Abstract:
A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V.<>
Date of Conference: 11-14 December 1994
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-2111-1
Print ISSN: 0163-1918
