A delay line loop for frequency synthesis of de-skewed clock

For microprocessors operating at 50 MHz or more, it is important to generate the internal clock (CLK) signal with minimal skew relative to the system clock, XCLK. In addition, speed improvements of silicon technology enable internal microprocessor clocking at a faster rate than the external bus. In this paper a fully-integrated delay line loop (DLL) clock generator circuit is used to perform frequency synthesis multiplication by N(f/sub CLK/=N/spl middot/f/sub XCLK/) of a de-skewed 50% duty-cycle CLK. The DLL offers mostly-digital implementation of an analog function with robustness and simplicity. The first version of the DLL was fully integrated on a RISC microprocessor chip and, later, on a cache-controller chip.<>