Abstract:
The authors describe a 10-b, 100-Ms/s ADC (analog-to-digital converter) with a pipelined subranging scheme, a sample-and-hold amplifier with 7.6-ns acquisition time, and ...Show MoreMetadata
Abstract:
The authors describe a 10-b, 100-Ms/s ADC (analog-to-digital converter) with a pipelined subranging scheme, a sample-and-hold amplifier with 7.6-ns acquisition time, and a 94-dB, 335-MHz op amp, enabling it to operate with 950-mW power dissipation from a single -5 V power supply. The design consists of sample-and-hold amplifiers, a coarse 6-b flash ADC, a fine 5-b flash ADC, a digital-to-analog converter, an analog subtractor, a register, and a digital adder with an error-correction function. The ADC is fabricated using a 0.8- mu m BiCMOS process featuring a double-layer polysilicon capacitor. The signal-to-noise-plus-distortion ratio as a function of input frequency at a 100-Ms/s conversion rate is shown.<>
Date of Conference: 24-26 February 1993
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-7803-0987-1
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1.
B. Zojer, "A 10b 75MHz Subranging A/D Converter", ISSCC DIGEST OF TECHNICAL PAPERS, 1990-Feb.
2.
C. Lane, "A 10-BIT 60 MSPS FLASH ADC", Proceedings of BCTM, pp. 44-47, 1989-Sept.
3.
M. Yotsuyanagi, "A 12Bit5usec CMOS Recursive ADC with 25mW Power Consumption", Proceedings of CICC, pp. 6.4.1-4, 1989-May.
4.
K. Sone, "An 8-bit 20MHz Subranging ADC with Internal Clamp and S/H Circuits", ICCE Digest of Technical Papers, 1990-June.
