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On the synthesis of MVL functions for current-mode CMOS circuits implementation | IEEE Conference Publication | IEEE Xplore

On the synthesis of MVL functions for current-mode CMOS circuits implementation


Abstract:

Four-valued, one-variable multivalued logic (MVL) functions are synthesized using current-mode CMOS logic (CMCL) circuits. Use is made of the fact that in CMCL, addition ...Show More

Abstract:

Four-valued, one-variable multivalued logic (MVL) functions are synthesized using current-mode CMOS logic (CMCL) circuits. Use is made of the fact that in CMCL, addition of logic values (represented using discrete current values) can be performed at no cost and that negative logic values are readily available by reversing the direction of current flow. A synthesis procedure that is based on the cost-table approach is proposed. The procedure results in less expensive (in terms of the number of transistors needed) realizations than those achieved using existing techniques.<>
Date of Conference: 27-29 May 1992
Date Added to IEEE Xplore: 06 August 2002
Print ISBN:0-8186-2680-1
Conference Location: Sendai, Japan
Citations are not available for this document.

Cites in Papers - |

Cites in Papers - IEEE (7)

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1.
Mark H. Nodine, Craig M. Files, "A Mature Methodology for Implementing Multi-Valued Logic in Silicon", 38th International Symposium on Multiple Valued Logic (ismvl 2008), pp.2-7, 2008.
2.
M. Abd-El-Barr, L. Al-Awami, "Iterative-based minimization of unary 4-valued functions for current-mode CMOS realization", Proceedings. 34th International Symposium on Multiple-Valued Logic, pp.315-320, 2004.
3.
M. Abd-El-Barr, A. Al-Mutawa, "A new improved cost-table-based technique for synthesis of 4-valued unary functions implemented using current-mode CMOS circuits", Proceedings 31st IEEE International Symposium on Multiple-Valued Logic, pp.15-20, 2001.
4.
M. Abd-El-Barr, A. Al-Mutawa, "Cost-analysis of 4-valued unary functions implemented using current-mode CMOS circuits", Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), pp.215-220, 2000.
5.
G.E. Beers, L.K. John, "A novel memory bus driver/receiver architecture for higher throughput", Proceedings Eleventh International Conference on VLSI Design, pp.259-264, 1998.
6.
Yeong-Jar Chang, Chung Len Lee, "Synthesis of multi-variable MVL functions using hybrid mode CMOS logic", Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94), pp.35-41, 1994.
7.
Hui Min Wang, Chung Len Lee, J.E. Chen, "Algebraic division for multilevel logic synthesis of multi-valued logic circuits", Proceedings of 24th International Symposium on Multiple-Valued Logic (ISMVL'94), pp.44-51, 1994.

Cites in Papers - Other Publishers (3)

1.
L. WANG, X. CHEN, A. E. A. ALMAINI, "Modulo correlativity and its application in a multiple valued logic system", International Journal of Electronics, vol.85, no.5, pp.561, 1998.
2.
JIZHONG SHEN, P. DOUGLAS TOUGAW, "Design of symmetric ternary current-mode CMOS Schmitt inverter", International Journal of Electronics, vol.85, no.4, pp.477, 1998.
3.
Xiexiong Chen, Claudio Moraga, "Design of multivalued circuits based on an algebra for current-mode CMOS multivalued circuits", Journal of Computer Science and Technology, vol.10, no.6, pp.564, 1995.
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