INTRODUCTION
In low-power designs in 120nm CMOS, where low supply voltage is essential, rail-to-rail inputs are desirable. As a core and fundamental block of the analog section, many operational amplifiers also require the rail-to-rail input stage. This leads to a favourable signal-to-noise ratio in the analog section of a system-on-chip. Moreover, a noisy environment, in which other factors than electronic noise dominate the signal quality, may also call for rail-to-rail construction. Additionally, constant small-and large-signal behavior over the entire common-mode input range becomes indispensable in design of rail-to-rail input, because the inconstant transconductance and slew rate of an operational amplifier cannot keep a fixed unity gain frequency and will further launch issues in behavioral modelling for the analog cells in the system level[1], [6]. However, due to the transistor threshold voltage of about 0.4V and the supply voltage of 1.5V at maximum, the common-mode input voltage range of conventional op-amp topologies in 120nm CMOS is limited to about 0.2V to 0.4V, which is unacceptable for many applications.