Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs

A digital background calibration technique is proposed to correct for the linearity error due to capacitor mismatches in pipelined analog-to-digital converters (ADCs). During the normal ADC operation, it randomly swaps the feedback capacitor with the sampling capacitor(s) in the multiplying digital-to-analog converter (MDAC) of each pipeline stage in the pipelined ADC. The capacitor-mismatch errors in all pipeline stages are then concurrently measured and corrected in the digital domain. The proposed technique can be utilized in both single-bit and multibit MDACs. Owing to its simple iterative algorithm for capacitor-mismatch error calibration, its implementation requires minimal additional digital hardware. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-plus-distortion ratio is improved from 10 to 12.5bits and the spurious-free dynamic range is increased from 65 to 95 dB, in a 13-bit pipelined ADC with sigma=0.25% capacitor mismatches

I. Introduction

The linearity of a pipelined analog-to-digital converter (ADC) is primarily degraded by the linearity errors in its pipeline stages. Consider a typical pipeline stage with digital redundancy [1], as depicted in Fig. 1. In a switched-capacitor circuit implementation, the primary sources of linearity errors are: 1) the gain errors in the residue amplifier, due to the finite gain and dynamic effects of its operational amplifier [2]; and 2) the nonlinearity in the digital-to-analog subconverter (sub-DAC), due to capacitor-mismatch errors. Compared to gain errors, capacitor-mismatch errors have a significantly more degrading effect on the overall linearity of the pipeline stage [1], [3].