Combined image signal processing for CMOS image sensors

This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have various benefits compared with charge-coupled devices (CCDs), the images obtained from CISs have much lower quality than those from CCDs. To improve the quality of CIS images, it is required to do reproducing and enhancing processings such as color interpolation, white balancing, color correction, gamma correction and color conversion. They are implemented individually in most conventional designs though they have similar functional characteristics. In this proposed structure, the gamma correction block is moved to the front in order to combine several image signal processings into one block. An efficient compensation scheme is also proposed to reduce the errors caused by the moving of the nonlinear gamma correction. A prototype CIS image signal processor is implemented in Verilog-HDL and synthesized with 0.18/spl mu/m standard cell library. Experimental results show that the proposed structure reduces area and power consumption by 23.8% and 31.1%, respectively.

I. Introduction

According to the recent requirements of multimedia applications, digital still and video cameras are rapidly becoming widespread. They are enabling many new applications such as PC cameras, digital cameras integrated into cell phones and PDAs, intelligent toys, and so on. Most imaging systems have used charge-coupled devices (CCDs) [1], [2] to capture images because the image sensor plays a vital role in the quality of images. However, it is not easy for CCDs to be integrated with other functions. In addition, they are consuming high power.