Self-sampled vernier delay line for built-in clock jitter measurement

For high-speed analog and mixed signal circuits, on-chip clock jitter measurement has been a challenge in recent years. Circuit resolution, chip area, and frequency range are critical specification for built-in-test (BIT) circuit design. In order to fulfil these requirements, the self-sampled Vernier delay line (VDL) structure is proposed. Comparing with traditional VDL structure, there is no more jitter free sample clock used in this design. When the proposed circuit is designed in 14 ps circuit resolution, only 500/spl mu/m*750/spl mu/m chip area is used for 100 MHz to 400 MHz measurement range in TSMC 0.35/spl mu/m CMOS process.

I. Introduction

For high-speed circuit, clock jitter has been one of the most important parameters in evaluating the circuit performance. Traditionally, clock jitter measurements rely on the external equipments, like spectrum analyzer, ATE, real-time sampling oscilloscope and dedicated jitter instrumentation [1]. However, with the increase of clock frequency, several unexpected problems make equipment-based clock jitter measurements become more and more difficult. For example, the probe's loading effect distorts the tested clock signal and sometimes makes the wrong measurement result.