Abstract:
In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, thes...Show MoreMetadata
Abstract:
In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT'algorithms in the light of these constraints.
Published in: IEEE Transactions on Computers ( Volume: C-33, Issue: 5, May 1984)
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Cites in Papers - IEEE (168)
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1.
Luis A. Garcia-Astudillo, Almudena Lindoso, Luis Entrena, "Error Mitigation Using Optimized Redundancy for Composite Algorithms in FPGAs", IEEE Transactions on Aerospace and Electronic Systems, vol.60, no.2, pp.2143-2152, 2024.
2.
Pedro Paz, Mario Garrido, "A 5.2-GS/s 8-Parallel 1024-Point MDC FFT", 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), pp.1-6, 2023.
3.
Ignacio Amat Hernández, Juan A. López, "Any-Radix Efficient Fully-Parallel Implementation of the Fast Fourier Transform on FPGAs", 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), pp.1-6, 2023.
4.
Aditi Paul, Shaik Rafi Ahamed, Roy Paily Palathinkal, "ASIC and FPGA Implementation of Radix-22 32-point MDC-FFT Architecture", 2023 IEEE Silchar Subsection Conference (SILCON), pp.1-6, 2023.
5.
Xiao Zhou, Xuerong Chen, Yi He, Xingang Mou, "A Flexible-Channel MDF Architecture for Pipelined Radix-2 FFT", IEEE Access, vol.11, pp.38023-38033, 2023.
6.
Luis A. García-Astudillo, Luis Entrena, Almudena Lindoso, Honorio Martín, "Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique", IEEE Access, vol.10, pp.20643-20651, 2022.
7.
Luis A. García-Astudillo, Almudena Lindoso, Luis A. Entrena, Honorio Martín, Mario García-Valderas, Pedro Martín-Holgado, "Analyzing Scaled Reduced Precision Redundancy for Error Mitigation Under Proton Irradiation", IEEE Transactions on Nuclear Science, vol.69, no.7, pp.1485-1491, 2022.
8.
A. Manjarres Garcia, C. Osorio Quero, J. Rangel-Magdaleno, J. Martinez-Carranza, D. Durini Romero, "Parallel-Pipeline Fast Walsh-Hadamard Transform Implementation Using HLS", 2021 International Conference on Field-Programmable Technology (ICFPT), pp.1-4, 2021.
9.
Jinshan Yue, Yongpan Liu, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, "STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration", IEEE Journal of Solid-State Circuits, vol.56, no.6, pp.1936-1948, 2021.
10.
Mario Garrido, Pedro Malagón, "The Constant Multiplier FFT", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.68, no.1, pp.322-335, 2021.
11.
Jian Wang, Songting Li, "A Memory-Reduced Frequency Estimator for the Measurement of Sinusoidal Signal", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.68, no.3, pp.1038-1042, 2021.
12.
Zhenhao Ji, Yahui Ji, Bolei Wang, Feifei Gao, Huizheng Wang, Chuan Zhang, "A New Uplink Channel Estimation Architecture for Massive MIMO Systems with PDMA", 2019 IEEE 13th International Conference on ASIC (ASICON), pp.1-4, 2019.
13.
Mahmoud Nazmy, Omar Nasr, Hossam Fahmy, "A Novel Generic Low Latency Hybrid Architecture for Parallel Pipelined Radix-2k Feed Forward FFT", 2019 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, 2019.
14.
AbdolVahab Khalili Sadaghiani, Samad Sheikhai, "Hardware Implementation of High Speed Bartlett Spectral Density Estimator Based on R4MDC FFT", 2019 27th Iranian Conference on Electrical Engineering (ICEE), pp.1518-1522, 2019.
15.
Ahmed Elshafiy, Mohammed A. El-Motaz, Mohamed E. Farag, Omar A. Nasr, Hossam A. H. Fahmy, "On Optimization of Mixed-Radix FFT: A Signal Processing Approach", 2019 IEEE Wireless Communications and Networking Conference (WCNC), pp.1-6, 2019.
16.
Basant K. Mohanty, Pramod Kumar Meher, "Area–Delay–Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.66, no.3, pp.1042-1050, 2019.
17.
V Monica, S L Gangadharaiah, C K Narayanappa, "FPGA Based Efficient Feed forward FFT Architecture", 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), pp.1692-1697, 2018.
18.
Kazi Nikhat Parvin, Md. Zakir Hussain, "Impact of radices for the design of efficient FFT processor", 2018 2nd International Conference on Inventive Systems and Control (ICISC), pp.950-954, 2018.
19.
Mario Garrido, Shen-Jui Huang, Sau-Gee Chen, "Feedforward FFT Hardware Architectures Based on Rotator Allocation", IEEE Transactions on Circuits and Systems I: Regular Papers, vol.65, no.2, pp.581-592, 2018.
20.
Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham, "A Low-Power Hybrid Adaptive CORDIC", IEEE Transactions on Circuits and Systems II: Express Briefs, vol.65, no.4, pp.496-500, 2018.
21.
Benjamin Shokry, Mohamed Dessouky, Mona Safar, M. Watheq El-Kharashi, "A dynamically configurable-radix pipelined FFT algorithm for real time applications", 2017 12th International Conference on Computer Engineering and Systems (ICCES), pp.402-407, 2017.
22.
Kazi Nikhat Parvin, Md. Zakir Hussain, Md. Ali Ghazi Islam, "Impact of datapath unit for an efficient implementation of FFT processor", 2017 International Conference on Energy, Communication, Data Analytics and Soft Computing (ICECDS), pp.2748-2753, 2017.
23.
Carl Ingemarsson, Petter Källström, Fahad Qureshi, Oscar Gustafsson, "Efficient FPGA Mapping of Pipeline SDF FFT Cores", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.25, no.9, pp.2486-2497, 2017.
24.
Deepika Hiremath, B. Rajeshwari, "Implementation of Pipelined Radix-2 FFT using SDC and SDF architecture", 2016 IEEE Region 10 Conference (TENCON), pp.1660-1663, 2016.
25.
Nhan Nguyen-Thanh, Han Le-Duc, Duc-Tuyen Ta, Van-Tam Nguyen, "Energy efficient techniques using FFT for deep convolutional neural networks", 2016 International Conference on Advanced Technologies for Communications (ATC), pp.231-236, 2016.
26.
A. Ramakrishna, N Balaji, P. Srihari, "An efficient and enhanced memory based FFT processor using radix 16 booth with carry skip adder", 2016 International Conference on Signal Processing, Communication, Power and Embedded System (SCOPES), pp.1608-1612, 2016.
27.
P. V. Karthik, G. Bhrigu Rishi, G Chandu Sagar, "High speed FFT processor consuming optimal power", 2016 International Conference on Inventive Computation Technologies (ICICT), vol.3, pp.1-7, 2016.
28.
Junjie Zhang, Zehua Tang, Roger Giddings, Qi Wu, Weilong Wang, Bingyao Cao, Qianwu Zhang, J.M. Tang, "Stage-Dependent DSP Operation Range Clipping-Induced Bit Resolution Reductions of Full Parallel 64-Point FFTs Incorporated in FPGA-Based Optical OFDM Receivers", Journal of Lightwave Technology, vol.34, no.16, pp.3752-3760, 2016.
29.
Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham, Trong-Thuc Hoang, Duc-Hung Le, "A parallel pipeline CORDIC based on adaptive angle selection", 2016 International Conference on Electronics, Information, and Communications (ICEIC), pp.1-4, 2016.
30.
Jian Wang, Chunlin Xiong, Kangli Zhang, Jibo Wei, "A Mixed-Decimation MDF Architecture for Radix- 2^{k} Parallel FFT", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.24, no.1, pp.67-78, 2016.
Cites in Papers - Other Publishers (66)
1.
A. Padmavathi, G. L. Sumalata, "Area Efficient Design of In-Place RFFT Scaling for OFDM Applications", Advances in Signal Processing, Embedded Systems and IoT, vol.992, pp.673, 2023.
2.
Hongyang Zhao, Wangwei Hui, Qing Ye, Kaicheng Huang, Qiushuai Shi, Jianguo Tian, Wenyuan Zhou, "Parallel Fourier ptychographic microscopy reconstruction method based on FPGA", Optics Express, vol.31, no.3, pp.5016, 2023.
3.
Mohammed Salman Ahmed, Md. Kalesha, Andleeb Zahra, Zia Abbas, "Approximate Toom–Cook FFT with sparsity aware error tuning in a shared memory architecture", Integration, 2022.
4.
Rajasekhar Turaka, S. Ravi Chand, Tavanam Venkata Rao, V. Kumara Swamy, "FPGA Implementation of Radix-2 Pipelined FFT Algorithm for High-throughput Applications", Advances in Electrical and Computer Technologies, vol.881, pp.753, 2022.
5.
Hongyang Zhao, Wangwei Hui, Qing Ye, Kaicheng Huang, Qiushuai Shi, Jianguo Tian, Wenyuan Zhou, "High-performance heterogeneous FPGA data-flow architecture for Fourier ptychographic microscopy", Applied Optics, vol.61, no.6, pp.1420, 2022.
6.
Bo Yuan, Lingyi Huang, Boyang Zhang, "Hardware Architecture for Deep Neural Network Accelerator", Wiley Encyclopedia of Electrical and Electronics Engineering, pp.1, 2022.
7.
Anatoly Belous, "Features of Designing Digital Processing Systems for Radiolocation Systems Based on Microprocessor VLSI Sets", Handbook of Microwave and Radar Engineering, pp.53, 2021.
8.
Mario Garrido, "A Survey on Pipelined FFT Hardware Architectures", Journal of Signal Processing Systems, 2021.
9.
Hung-Ju Lin, Chung-An Shen, "The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems", Journal of Signal Processing Systems, vol.93, no.1, pp.67, 2021.
10.
L.A. García-Astudillo, A. Lindoso, L. Entrena, H. Martín, M. García-Valderas, "Error sensitivity study of FFT architectures implemented in FPGA", Microelectronics Reliability, vol.126, pp.114298, 2021.
11.
Doru Florin Chiper, "A Structured Fast Algorithm for the VLSI Pipeline Implementation of Inverse Discrete Cosine Transform", Circuits, Systems, and Signal Processing, vol.40, no.11, pp.5351, 2021.
12.
G. Prasanna Kumar, B. T. Krishna, K. Pushpa, "Optimized Pipelined Fast Fourier Transform Using Split and Merge Parallel Processing Units for OFDM", Wireless Personal Communications, vol.117, no.4, pp.3067, 2021.
13.
Mario Garrido, Fahad Qureshi, Jarmo Takala, Oscar Gustafsson, "Hardware architectures for the fast Fourier transform", Handbook of Signal Processing Systems, pp.613, 2019.
14.
M. I. ANJU, J. MOHAN, M. I. BEENA, "FPGA IMPLEMENTATION OF RADIX-2 FFT PROCESSOR BASEDON CORDIC ALGORITHM FOR ELECTROMYOGRAPHY", i-manager's Journal on Digital Signal Processing, vol.7, no.2, pp.15, 2019.
15.
V. Kitsakis, K. Nakos, D. Reisis, N. Vlassopoulos, "Parallel Memory Accessing for FFT Architectures", Journal of Signal Processing Systems, 2018.
16.
Cheng Yang, Weidong Bao, Xiaomin Zhu, Ji Wang, Wenhua Xiao, Algorithms and Architectures for Parallel Processing, vol.11336, pp.293, 2018.
17.
Carl Ingemarsson, Oscar Gustafsson, "SFF—The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture", Journal of Signal Processing Systems, vol.90, no.11, pp.1583, 2018.
18.
Hong-Thu NGUYEN, Xuan-Thuan NGUYEN, Cong-Kha PHAM, "A Low-Latency Parallel Pipeline CORDIC", IEICE Transactions on Electronics, vol.E100.C, no.4, pp.391, 2017.
19.
Mohamed Asan Basiri M, Noor Mahammad Sk, "Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform", Integration, vol.55, pp.43, 2016.
20.
Atin Mukherjee, Amitabha Sinha, Debesh Choudhury, "A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation", ACM SIGARCH Computer Architecture News, vol.42, no.4, pp.1, 2016.
21.
Anatolij Sergiyenko, Anastasia Serhienko, "Modules for Pipelined Mixed Radix FFT Processors", International Journal of Reconfigurable Computing, vol.2016, pp.1, 2016.
22.
Hong-Thu Nguyen, Xuan-Thuan Nguyen, Trong-Thuc Hoang, Duc-Hung Le, Cong-Kha Pham, "Low-resource low-latency hybrid adaptive CORDIC with floating-point precision", IEICE Electronics Express, vol.12, no.9, pp.20150258, 2015.
23.
J.J. Zhang, K. Wang, W.Y. Yuan, B.Y. Cao, R.P. Giddings, M. Wang, J.M. Tang, "Stage-dependent Minimum Bit Resolution Maps of Full-parallel Pipelined FFT/IFFT for Real-time Optical OFDM Transceivers", Asia Communications and Photonics Conference 2014, pp.AW3E.2, 2014.
24.
Deepak Dasalukunte, Viktor Öwall, Fredrik Rusek, John B. Anderson, "IOTA Pulse-Shaping Filters in FTN Multi-Carrier Systems", Faster than Nyquist Signaling, pp.107, 2014.
25.
Junjie Zhang, Wenyan Yuan, Kai Wang, Bingyao Cao, Roger P. Giddings, Min Wang, Jianming Tang, "Stage-dependent minimum bit resolution maps of full-parallel pipelined FFT/IFFT architectures incorporated in real-time optical orthogonal frequency division multiplexing transceivers", The Journal of Engineering, vol.2014, no.8, pp.469-476, 2014.
26.
Shingo YOSHIZAWA, Yoshikazu MIYANAGA, "Hardware Implementation of FFT Processors for Wireless Communications", IEICE ESS Fundamentals Review, vol.7, no.2, pp.116, 2013.
27.
Seung-Won Yang, Jong-Yeol Lee, "A new low-power butterfly unit for single-path delay feedback FFT architectures", IEICE Electronics Express, vol.10, no.24, pp.20130640, 2013.
28.
CuiMei Ma, He Chen, JiYang Yu, Teng Long, "A novel conflict-free parallel memory access scheme for FFT constant geometry architectures", Science China Information Sciences, vol.56, no.4, pp.1, 2013.
29.
Nishant Kumar Giri, Amitabha Sinha, "FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT", ACM SIGARCH Computer Architecture News, vol.40, no.2, pp.28, 2012.
30.
Bruno Fernandes, Helena Sarmento, "FPGA implementation and testing of a 128 FFT for a MB-OFDM receiver", Analog Integrated Circuits and Signal Processing, vol.70, no.2, pp.241, 2012.
