Functional Constraints vs. Test Compression in Scan-Based Delay Testing

We present an approach to prevent over testing in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many positions as possible unspecified in order to facilitate test compression. The method is independent of the employed delay fault model, ATPG algorithm and test compression technique, and it is easy to integrate into an existing flow. Experimental results emphasize the severity of over testing in scan-based delay test. Influence of different functional constraints on the amount of the required test data and the compression efficiency is investigated. To the best of our knowledge, this is the first systematic study on the relationship between over testing prevention and test compression

1 Introduction

Extensive use of design for testability (DFT) techniques, including scan and test points, and non-nominal test methods such as low-voltage test and test [1], [2] lead to overtesting, i.e., the IC is demonstrated to fail, but under conditions which cannot occur in its normal operation mode. One reason for overtesting is the presence of latent defects, which are too small to cause a failure under nominal conditions or logically redundant. A further reason is the elevated level of IR drop and crosstalk effects which is caused by atypical power consumption during test that does not correspond to the power consumption profile in normal operation [3]. Last but not least, behavior which does not contradict the specification could be classified as “faulty behavior” by the test process if design tricks such as cycle stealing are employed.