New method for threshold voltage extraction of high-voltage MOSFETs based on gate-to-drain capacitance measurement

This letter reports on the extraction of the threshold voltage of laterally diffused MOS transistors. A clear analysis of the device physics is performed, highlighting the correlation between the change of the electron charge distribution along the channel and the device capacitance variations when the gate voltage is swept. Using numerical simulations, it is shown that the peak of the gate-to-drain capacitance is related to the transition of the surface from weak to moderate inversion in the intrinsic MOS transistor at the location of the maximum doping concentration, which corresponds to the threshold voltage of the device according to the MOS theory. Comparison between conventional I/sub D///spl radic/g/sub m/ extraction and the new proposed capacitance peak method is performed on both technology computer-aided design simulations and measurements in order to confirm the new experimental technique and related theory.

I. Introduction

With the development of both advanced low-and high-voltage microelectronic MOSFET devices, many works in the literature report on threshold voltage extraction, with a dominance of the techniques specific to low-voltage devices [1]–[4]. Despite these efforts, there is a lack of simple extraction methods related to the physics of the device, especially for some particular architectures of high-voltage devices such as the laterally diffused MOS (LDMOS) transistors. Many extraction methods are based on mathematical speculations of some developed models with several degrees of complexity and, sometimes, questionable degree of accuracy. For the characterization and modeling of high-voltage devices, the low-voltage extraction techniques are, in most cases, directly applied without taking into account their special architecture and physics. In this letter, we propose a simple extraction procedure for the evaluation of the threshold voltage of laterally diffused MOSFETs (LDMOSFETs) based on the bias-dependent charge distribution inside the device. The proposed technique is independent of series resistances or mobility reduction with the gate voltage that impact any current-based extraction. Numerical simulations and experimental results are used to confirm the proposed theory and to demonstrate the extraction procedure.